陈松 副教授

2000年7月毕业于西安交通大学获学士学位；2005年7月毕业于清华大学计算机科学与技术系获硕士、博士学位；2005年8月至2009年3月在日本早稻田大学相继任客座副研究员、客座讲师、助理教授；2012年9月起加入中国科学技术大学信息学院电子科学与技术系，任副教授。在超大规模集成电路计算机辅助设计领域从事多年研究，共计发表/合作发表论文70多篇，其中期刊论文20篇，SCI检索18篇，EI检索会议论文40多篇，授权专利5项。在早稻田大学期间指导毕业的硕士生近20名，合作指导博士生毕业3名。目前讲授研究生专业课《超大规模集成电路设计优化》。

研究领域：

1) VLSI计算机辅助设计：物理设计、片上网络合成、高层次综合等; 

2) VLSI及FPGA应用：计算机视觉嵌入式系统、实时多媒体处理系统等; 

3) 新兴技术设计自动化：微流体生物芯片、量子电路等;

获奖情况: 

IEEE Asia Pacific Conference on Circuits and Systems 2006 最佳论文奖

论文著作：

期刊论文:

• 1. Nan Wang, Song Chen, Wei Zhong, Nan Liu, Takeshi Yoshimura, “Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol E97-A, No.8, pp.1-11(accepted), No.8, 2014.

• 2. Wei Zhong, Song Chen, Bo Huang, Takeshi Yoshimura, and Satoshi Goto, “Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips”, IEICE Transactions on on Fundamentals of Electronics, Communications and Computer Sciences,, Vol. E96-A, No.6, pp. 1174- 1184, 2013.

• 3. Nan Liu, Song Chen, and Takeshi Yoshimura, “ Resource-aware Multi-layer Floorplanning for Partially Reconfigurable FPGAs ”, IEICE Transactions on Electronics, Vol.E96-C, No.4, pp 501-510, 2013.

• 4. Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong and Satoshi Goto,  Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips, IEICE Transactions on Electronics, Vol.E95-C, NO.4, pp.535-545, April,2012.

• 5. Song Chen and T. Yoshimura. Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints. Integration, the VLSI journal, 43(4), pp.378-388, 2010. binary package

• 6. Song Chen, Liangwei Ge, Mei-Fang Chiang, Takeshi Yoshimura, “ Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, No.4, pp.1080-1087, 2009.

• 7. L. Ge, Song Chen, and T. Yoshimura, “ Exploration of schedule space by random walk,” IPSJ Transactions on System LSI Design Methodology, vol. 2, pp.30-42, Feb. 2009.

• 8. Song Chen and T. Yoshimura, “ Fixed-outline floorplanning: Enumerating block positions and a new objective function for calculating area costs,” IEEE Transactions On CAD of Integrated Circuits and Systems, vol.27, no. 5, pp.858-871, 2008. binary package

• 9. Song Chen, S. Dong, X. Hong, and C. Cheng, “Vlsi block placement with alignment constraints,” IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 53, no. 8, pp. 622-626, 2006.

• 10. Y. Ma, X. Hong, S. Dong, Song Chen, and et al, “ Buffer planning as an integral part of floorplanning with consideration of routing congestion,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol.24, no.4, pp.609-621, 2005.

会议论文:

• 1. Zhen Meng, Song Chen and Lu Huang, Irregularly Shaped Voltage Islands Generation with Hazard and Heal Strategy, IEEE 16th International Symposium on Quality Electronic Design (ISQED), San Clara, USA, March, 2015, pp.1-4.

• 2. Qi Xu, Song Chen and Bin Li, Ant system based 3D fixed-outline floor planning, IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014 pp.1-3, October 2014.

• 3. Nan Wang, Song Chen and Takeshi Yoshimura, Min-Cut Based Leakage Power Aware Scheduling in High-Level Synthesis, IEEE International Symposium on Quality Electronic Design (ISQED), San Clara, USA, March, 2013.

• 4. Jianchang Ao, Sheqin Dong, Song Chen and Satoshi Goto, “Delay-Driven Layer Assignment in Global Routing under Multi-tier Interconnect Structure”, ACM International Symposium on Physical Design (ISPD), Nevada, USA, March, 2013.

• 5. Nan Wang, Song Chen, Takeshi Yoshimura, Yuhuan Sun, Mobility Overlap-Removal Based Leakage Power Aware Scheduling in High-Level Synthesis, IEEE International Symposium on Circuits and Systems(ISCAS), Beijing, China, May, 2013.

• 6. Bo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura, Topology-Aware Floorplanning for 3D Application-Specific Network-on-Chip Synthesis”, IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, May, 2013.

• 7. Cong Hao, Song Chen, Takeshi Yoshimura, “Network Simplex Method Based Multiple Voltage Scheduling in Power-Efficient High-Level Synthesis”, ACM/IEEE Asia and Soutch Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 2013, pp.237-242.

• 8. Song Chen, Xiaolin Zhang, Takeshi Yoshimura, “Practically Scalable Floorplanning with Voltage Island Generation”, ACM The International Symposium on Low Power Electronics and Design (ISLPED), July, Redondo, USA, 2012.

• 9. Tao Lin, Sheqin Dong, Song Chen, and Satoshi Goto, “Linear Optimal One-Sided Single-Detour Algorithm for Untangling Twisted Bus”, ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2012.

• 10. Wei Zhong, Song Chen, Fei Ma, Takeshi Yoshimura, and Satoshi Goto, “Floorplanning driven network-on-chip synthesis for 3-D SoCs,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Brazil, pp. 1203-1206, 2011.

• 11. Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, S. Goto, Novel and efficient min cut based voltage assignment in gate level, 12th IEEE International Symposium on Quality Electronic Design (ISQED), pp.1-6, 14-16 March 2011.

• 12. B. Yu, S. Dong, Song Chen, and S. Goto, “Floorplanning and topology generation for application-specific network-on-chip”, In IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 535 –540, 2010.

• 13. T. Lin, S. Dong, B. Yu, Song Chen, and S. Goto, “A revisit to voltage partitioning problem”, In Proceedings of the 20th ACM Great lakes symposium on VLSI, pp. 115--118. New York, NY, USA, 2010.

• 14. Wei Zhong, Song Chen, and T. Yoshimura. Whitespace Insertion for Through-Silicon Via Planning on 3-D SoCs. In Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pages 913--916. Paris, France, May 2010.

• 15. J. Liang, Song Chen, and T. Yoshimura, “Redundant via insertion based on conflict removal,” in Proc. Of IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). Nov. 2010, pp. 794-796.

• 16. Song Chen, Y. Yao, and T. Yoshimura, “A dynamic programming based algorithm for post-scheduling frequency assignment in energy-efficient high-level synthesis,” in International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Shanghai, China, Nov. 2010, pp. 797-799.

• 17. Song Chen, Z. Xu, and T. Yoshimura, “A generalized v-shaped multilevel method for large scale floorplanning,” in The 9th IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, USA , March 2009, pp 734-739.

• 18. Song Chen and T. Yoshimura, “A stable fixed-outline floorplanning method,” in Proc. ACM International Symposium on Physical Design (ISPD), Austin,Texas, USA, March 2007. pp.119-126.

• 19. Song Chen and T. Yoshimura, “On the number of 3-d ic floorplan configurations and a solution perturbation method with good convergence,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore, December 2006.